In a typical computer-related apparatus, there is usually at least a system bus, system memory, a processor and a controller or application in communication with one another to affect the execution of certain data transactions for the device. In many of such computer and data processing systems, the main active memory is typically random access memory (RAM) and often is a dynamic random access memory (DRAM).
In such devices, it has become common for a data transaction to be sizeable such that the demand of the transaction access (e.g., command, read, write, store, etc.) may attempt to demand near exclusive utilization of the available shared memory resources in order to execute the particular data transaction. Though many system bus standards provide for a single command transferring a significant amount of data by a single operation, doing so may cause diminished system-level performance and cause other tasks to be handled late or with delay. The effect of such operations may result in serial-like performances of specific tasks for memory utilization which is unacceptable for effective device operations in today's environments. Accordingly what is needed is a system and method to address these issues.